%FILENAME%
vtr-8.0.0-4-x86_64.pkg.tar.zst

%NAME%
vtr

%BASE%
vtr

%VERSION%
8.0.0-4

%DESC%
Verilog to Routing -- Open Source CAD Flow for FPGA Research

%CSIZE%
6525293

%ISIZE%
20454327

%MD5SUM%
b1c9e264e765bb9e496a87906ac243a5

%SHA256SUM%
9faba96d6ecb95d5e5af5e542690f0075d0bc57d1f046b13562de7f167e4792e

%PGPSIG%
iQEzBAABCAAdFiEEFRnVq6Zb9vwrc8dWek52CV2KUuQFAmGhHAwACgkQek52CV2KUuRokwf/QO+MU/zbj0Cpi5kxGjA5i/5lnafogPMSGXg4zlrxsCMShTmo87NXhq9L5pQ/oyUtVEd1jGXYJ8jE+vZvs4FPYrDq7H/VcRqmguKN1DY9iyNl6DDtVt8KNLKMIGY+eYW+JqeZG3wNofa9vLWoDJZBJndQ6nauhrwqId46nbHlTE2yKY5N8hC1V+FlDpFXLDMaQPyfboZ0FTpsCpGnbxXeEeXq2FD+v+FCuyKC7WukVE4ovqUzpMUlOuja85mrPf2hVw2pvQVALZsUYQA/rN7Kwx2Z7UN7aydBogktWZ8Uei79/6hdh5CyKNOsSkEAlcob1oI8V6URQkuIM5yEJNzeSg==

%URL%
https://verilogtorouting.org

%LICENSE%
MIT

%ARCH%
x86_64

%BUILDDATE%
1637948324

%PACKAGER%
Antonio Rojas <arojas@archlinux.org>

%DEPENDS%
ctags
tbb

%MAKEDEPENDS%
cmake

