%FILENAME%
verilator-4.216-1-x86_64.pkg.tar.zst

%NAME%
verilator

%BASE%
verilator

%VERSION%
4.216-1

%DESC%
The fastest free Verilog HDL simulator

%CSIZE%
4859146

%ISIZE%
23651672

%MD5SUM%
60e988da152ac1a0b4fb400f970ad772

%SHA256SUM%
eb7dfa4d8d2896797b4c6075d716356ea5c633ac695f71580bcb2944ae4c1488

%PGPSIG%
iQIzBAABCAAdFiEEtZcfLFwQqaCMYAMPeGxj8zDXy5IFAmG1Ig0ACgkQeGxj8zDXy5LYOg//QqM/0cbq79qDh/IPVjxtf8QtiCNyg4Eqm9UvrOj31J1kiU4aPA1r5JtCC1ko2ftsf+KA2snNGCNYM+UbFpPElwUhzdBEuDQ50hOGbUPnm6p5BblPQc8rztd9oxQ2RTBujqhDFEWsrYX83fbIUmOfXcCMnb90sWtn2sPnnVrck4WacP4g1dPuInOw5jRlN3YpzYQwXl2IN8bkhEHNJ5/UPl/k/hLNn67i/Jr39kYGpfNcd5WFDEeqtLgXMB1Ms1CJLjzx8/LqLGL9NVWFWAfPOacVHGHKDLCaV1wVxRuD+u6c5KriEBvh7HJBEPzN7vdtdlSaVEoMEQqTjEFG1kxFjNB8Ew4nLmkttgdP6Qe6KlpGlJu5ny6aN1GmcdUv3cY9vsbPFh4vila6ru6x7Em7ka9rAnAZ98rDxU/mCiQNboY+yPUe9P5RYw4l9WVAgEDM00AxXQR+E7cKiERo9VcWYplh1cSdmzPq38xQ0GQgm9Ri4mZbf4s2/kVohfOGzDrgOUmiLhO5tyoOFT4gn2lk6N19lfQLMwJ+vh6Wk6AIzet3k0cxjqhY2OHCq+zd2CmVi/5zizNFw+0RwYusbyevGrCXz9Xrboi2aTMVeQ4QNkwgbrDT2ETKx+PAszT5pAzj+JvSad3tXttVXHdzXWCN2yrPmFtxR+X/vUw8g9QKUdQ=

%URL%
https://www.veripool.org/projects/verilator/wiki/Intro

%LICENSE%
LGPL

%ARCH%
x86_64

%BUILDDATE%
1639260577

%PACKAGER%
Felix Yan <felixonmars@archlinux.org>

%DEPENDS%
perl

%OPTDEPENDS%
systemc

%MAKEDEPENDS%
python
systemc

